1. Field of the Invention
The present invention relates generally to a self orthogonal decoding circuit and a self orthogonal decoding method. More particularly, the invention relates to a decoding method and a decoding circuit for a self orthogonal code as convolution code which is quite simple and easy to apply to systems.
2. Description of the Related Art
Self orthogonal code has been known as being quite simple and easy to apply for systems and has been widely applied in the field of satellite communication, optical communication or communication by a wire cable. However, in comparison with Viterbi decoding as most-probable decoding of the convolution code, the conventional self orthogonal code is lower in error correction performance.
A construction of the conventional decoder for self orthogonal code is illustrated in FIG. 25. In FIG. 25, there is illustrated a construction of the case of self orthogonal code in a coding ratio of 1/2. In this case, code generating polynomial expression is assumed to be:
 G1=1+X2+X5+X6  (1)
number of orthogonal is assumed to be four. Theoretical background of the self orthogonal code and detail of realizing method of the conventional decoder has been disclosed in Hideki Imai, “Coding Theory”, The Institute of Electronics. Information and Communication Engineers, March, 1990, pp 274 to 278.
In the self orthogonal code of coding ratio 1/2, check series of the same proportion to information series is added in the encoder to generate a transmission series, in which information series and check series are arranged alternately. The transmission series is output to a line. Then a reception series Y added an error to the transmission series is input to the decoder.
The conventional self orthogonal code decoder is constructed with a code Synchronization and serial/parallel converter circuit 7, a syndrome series generation circuit 8, an error value generation circuit 10 and an error correcting portion 9.
The reception series input to the decoder is input to the code synchronization and serial/parallel converter circuit 7. The code synchronization and serial/parallel converter circuit 7 establishes synchronization of the code and performs serial/parallel conversion of the reception series Y into the information series I and the check series P to output to the syndrome series generation circuit 8.
Code synchronization is performed on the basis of an error count value EC input from the error value generation circuit 10. For example, when the error count value EC is greater than or equal to a threshold value, out of code synchronization is judged to vary a phase of the parallel signal to be output to the syndrome series generation circuit 8. The syndrome series generation circuit 8 generates a syndrome series S on the basis of the information series I and the check series P input from the code synchronization and serial/parallel converter circuit 7.
A construction of the syndrome series generation circuit 8 is shown in FIG. 26. In FIG. 26, the syndrome series generation circuit 8 is constructed with first to sixth order information series registers 81-1 to 81-6 and an exclusive OR circuit 82.
The information series I is input to the first order information series register 81 and then shifted in sequential order from the second to sixth information series shift registers 81-2 to 81-6 at every occurrence of clock. The information series I thus delayed by the first to sixth information series shift registers 81-1 to 81-6 to be output to the error correcting portion 9 as delayed information series ID.
Number of stages of the information series registers corresponding to number of orders of the generation polynomial expression. The input information series I corresponds to (0)th order of the generation polynomial expression. Data corresponding to the order of the generation polynomial expression having coefficient other than 0 and the check series P are input to the exclusive OR circuit 82.
In the shown example, the generation polynomial expression has coefficients other than 0 in zeroth, second, fifth and sixth order. Therefore, information series I, outputs of the second, fifth and sixth information series registers and the check series P are input to the exclusive OR circuit 82.
The exclusive OR circuit 82 takes an exclusive OR of the input signal to output it to the error value generation circuit 10 as the syndrome series S.
The error value generation circuit 10 leads an error value on the basis of the syndrome series S input from the syndrome series generation circuit 8. A construction of the error value generation circuit 10 is illustrated in FIG. 27. In FIG. 27, the error value generation circuit 10 is constructed with zeroth to fifth syndrome registers 101-0 to 101-5, a majority decision judgment circuit 103, an error detection counter 104 and syndrome correcting exclusive OR circuit 101-1 to 102-3. Number of order of the syndrome registers corresponds to number of order of the generation polynomial expression.
The input syndrome series S corresponds to the highest order (sixth order) of the generation polynomial expression. Data corresponding to number of order of the expression polynomial expression having the coefficient other than zero, is input to the majority decision judgment circuit 103. Assuming the number of orthogonal is J, the judgment threshold value A of the majority decision judgment circuit 103 becomes:A=└J/2┘  (2)
The majority decision judgment circuit 103 makes judgment that error is caused when number of input signals having value “1” is greater than or equal to A, “1” is output as an error value E. When the majority decision judgment circuit 103 outputs “0” as the error value E with judgment that error is not caused when number of input signals having a value “1” is less than the judgment threshold value A.
Since the generation polynomial expression in the shown example has coefficients other than zero at zeroth, second, fifth and sixth order, outputs of the zeroth, second and fifth syndrome registers 101-0, 101-2 and 101-5 and the syndrome series S are input to the majority decision judgment circuit 103. Accordingly, the majority decision judgment circuit 103 has four input signals. The majority decision judgment circuit 103 makes judgment as error being caused when number of the input signals having values “1” is greater than or equal to three to output “1” as the error value E.
The syndrome series S is shifted from higher order syndrome register to lower order syndrome register at every occurrence of clock. It has been known that when error is detected in the majority decision judgment circuit 103 influence of the error is eliminated from the syndrome series S to achieve enhancement of error correction performance. In order to eliminate influence of error from the syndrome series S, the signal input to the majority decision judgment circuit 103 is inverted the value when the error is detected and then input to the lower order syndrome register.
More particularly, inversion of the values is performed by the syndrome correcting exclusive OR circuit 102-1 to 102-3. The syndrome correcting exclusive OR circuits 102-1 to 102-3 take the syndrome series S and the outputs of the fifth and second syndrome registers 101-5 and 101-2 as first input, and take the error value E as second input. The syndrome correcting exclusive OR circuit 102-1 to 102-3 takes an exclusive OR of the first input and the second input to output the results of exclusive OR operation to the fifth, fourth and first syndrome registers 101-5, 101-4 and 101-1.
The error detection counter 104 takes an error value E as input and counts number of error detected within a given period. The counter error count value EC is output to the code synchronization and serial/parallel converter circuit 7. The error correcting portion 9 makes correction of the delayed information series ID input from the error value generation circuit 10 on the basis of the error value E input from the syndrome series generation circuit 8 to output as a corrected information series IC.
While the foregoing conventional self orthogonal decoding circuit is simple in decoding and easy to apply for systems, it holds shortcoming in lower error correction performance in comparison with Viterbi decoding as most-probable decoding of the convolution code.